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Huawei’s new chip scaling law aims to sidestep ASML chokepoint but hurdles remain: analysts

If proven, the innovation marks a significant milestone for Huawei, which has been cut off from advanced semiconductor technology since 2019

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A concept illustration of a Huawei chip. Photo: Shutterstock Images
Coco Fengin Guangdong,Ann Caoin ShanghaiandIris Dengin Shenzhen

Huawei Technologies has engineered a workaround to one of China’s most crippling chipmaking bottlenecks, but analysts warn that the nation’s path to semiconductor independence is still constrained by manufacturing challenges.

The US-sanctioned tech giant on Monday introduced a new scaling law and a chip architecture designed to deliver products equivalent to an advanced 1.4-nanometre processing node by 2031.

If true, the innovation marks a significant milestone for Huawei, which has been cut off from advanced semiconductors, leading lithography machines from Dutch supplier ASML, and cutting-edge electronic design automation (EDA) tools since 2019.

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The company’s new Tau (τ) Scaling Law proposes a major shift in how chips are built. For decades, the industry advanced by physically shrinking transistors to pack more onto a silicon wafer. Huawei is betting instead on a concept called “time scaling”.

Rather than trying to make the hardware components smaller, the firm aims to boost performance by compressing the effective time constant (τ) – essentially speeding up how fast signals travel across devices, circuits and systems.

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Under this new path, improvements in lithography tooling – the critical chokepoint in China’s semiconductor ambitions – are “not necessary”, according to He Tingbo, chair of Huawei Scientist Committee and president of the company’s semiconductor business department.

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